1. Field of the Invention
The invention relates to the field of integrated circuit interconnections and, in particular, to structures and methods for vertically stacking chips for increased volume density without increased footprint.
2. Description of the Related Art
Modem electronic devices, such as computers and the like, typically include integrated circuits encapsulated in packages generally referred to generically as “chips”. Chips are generally planar structures and typically include a plurality of conducting pads disposed as surface contacts about a surface of the chip and/or “pins” along an edge thereof. The conducting pads generally interconnect to a plurality of interconnecting conductive traces that extend from the pads to the electronic devices within the chip and allow interconnection of the electronic devices to external circuits to allow a system level circuit.
With advances in semiconductor device processing has come a continuing increase in device count and density within chips and this has driven a corresponding increase in the count and density of the external conducting pads. Current technology places a limit on how small external contacts can be made and how closely they can be placed adjacent one another while still maintaining circuit integrity. Limits are imposed both by the limitations of machinery to form ever smaller conductive elements and the reduction in production yield as the limits are pushed.
An additional concern is an overall system level consideration of packaging. As previously mentioned, chips are generally planar structures with relatively thin, flat profile. A common practice has been to interconnect chips on another generally planar support structure often referred to as a “mother board”. However, the desire to provide the capability of integrated circuits to relatively small devices limits the extent to which multiple chips can be laterally interconnected while still fitting within the device. In addition, lateral extension and interconnection of chips tends to lead to relatively long interconnects between chips and thus between circuit components thus introducing propagation delays that can limit the practical speed of operation of the system level circuits.
From the foregoing, it can be appreciated that there is an ongoing need for structures and methods for interconnecting chips to increase circuit density without increasing the chip footprint and with minimal increase in interconnection length.